HD64F2357VF13 Datasheet, PDF (435/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T₂ state of a
TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed.
Figure 10-49 shows the timing in this case.
ø
Address
Write signal
Counter clear
signal
TCNT
TCNT write cycle
T₁
T₂
TCNT address
N
H'0000
Figure 10-49 Contention between TCNT Write and Clear Operations
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T₂ state of a TCNT write
cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10-50 shows the timing in this case.
ø
Address
Write signal
TCNT input
clock
TCNT
TCNT write cycle
T₁
T₂
TCNT address
N
M
TCNT write data
Figure 10-50 Contention between TCNT Write and Increment Operations
Rev.6.00 Oct.28.2004 page 405 of 1016
REJ09B0138-0600H