HD64F2357VF13 Datasheet, PDF (972/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCSR—Timer Control/Status Register
H'FFBC (W), H'FFBC (R)
WDT
Bit
:
7
6
5
4
OVF WT/IT TME
—
Initial value :
0
0
0
1
Read/Write : R/(W)^* R/W R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Clock Select
CKS2 CKS1 CKS0 Clock
Overflow period*
(when ø = 20 MHz)
0
0
0 ø/2 (initial value) 25.6µs
1 ø/64
819.2µs
1
0 ø/128
1.6ms
1 ø/512
6.6ms
1
0
0 ø/2,048
26.2ms
1 ø/8,192
104.9ms
1
0 ø/32,768
419.4ms
1 ø/131,072
1.68s
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
Timer Enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1 Watchdog timer mode: Generates the WDTOVF signal^*1 when
TCNT overflows*²
Notes: 1. The WDTOVF pin function is not available in the
F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, or
H8S/2390.
2. For details of the case where TCNT overflows in
watchdog time mode, see section 13.2.3, Reset
Control/Status Register(RSTCSR).
Overflow Flag
0 [Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1 [Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
The method for writing to TCSR is different from that for general registers to prevent accidental
overwriting. For details see section 13.2.4, Notes on Register Access.
Note: * Can only be written with 0 for flag clearing.
Rev.6.00 Oct.28.2004 page 942 of 1016
REJ09B0138-0600H