HD64F2357VF13 Datasheet, PDF (217/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is
performed, of the internal interrupt source selected by the data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer
factor setting does not issue an interrupt request to the CPU or DTC.
When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared
when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt
source should be cleared by the CPU or DTC transfer.
When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to
the CPU or DTC regardless of the DTA bit setting.
The state of the DTME bit does not affect the above operations.
Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the
internal interrupt source selected by the channel 1 data transfer factor setting.
Bit 11
DTA1
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the
internal interrupt source selected by the channel 0 data transfer factor setting.
Bit 9
DTA0
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 10 and 8—Reserved: Can be read or written to. Write 0 to these bits.
Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or
disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is
enabled for the channel.
If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is
cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1
again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI
interrupt, and transfer is not interrupted.
The conditions for the DTME bit being cleared to 0 are as follows:
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit
The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0
Rev.6.00 Oct.28.2004 page 187 of 1016
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