HD64F2357VF13 Datasheet, PDF (155/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data
alignment function, and when accessing external space, controls whether the upper data bus (D₁₅ to D₈) or lower data bus
(D₇ to D₀) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space)
and the data size.
8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D₁₅ to D₈) is always used for accesses. The amount of data that can be accessed at one time is one byte:
a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses.
Byte size
Upper data bus Lower data bus
D₁₅
D₈ D₇
D₀
Word size
1st bus cycle
2nd bus cycle
Longword size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space)
Rev.6.00 Oct.28.2004 page 125 of 1016
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