HD64F2357VF13 Datasheet, PDF (474/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.3.3 Timing of External RESET on TCNT
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in
TCR. The clear pulse width must be at least 1.5 states. Figure 12-7 shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12-7 Timing of External Reset
12.3.4 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12-8 shows the timing
of this operation.
ø
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 12-8 Timing of OVF Setting
Rev.6.00 Oct.28.2004 page 444 of 1016
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