HD64F2357VF13 Datasheet, PDF (961/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

SCR2—Serial Control Register 2
H'FF8A
Smart Card Interface 2
Bit
:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable
SCMR SMR SCR setting
SMIF C/A,GM CKE1 CKE0
SCK pin function
0
See SCI specification
1
0
0
0 ^{Operates as port input}
pin
1
0
0
1 ^{Clock output as SCK}
output pin
1
1
0
0
Fixed-low output as
SCK output pin
1
1
0
1 ^{Clock output as SCK}
output pin
1
1
1
0
Fixed-high output as
SCK output pin
1
1
1
1 ^{Clock output as SCK}
output pin
Transmit End Interrupt Enable
0 Transmit end interrupt (TEI) request disabled
1 Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1 Multiprocessor interrupts enabled
Receive data full interrupt (RXI) requests, receive error interrupt
(ERI) requests, and setting of the RDRF, FER, and ORER flags
in SSR are disabled until data with the multiprocessor bit set to
1 is received
Receive Enable
0 Reception disabled
1 Reception enabled
Transmit Enable
0 Transmission disabled
1 Transmission enabled
Receive Interrupt Enable
0 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request disabled
1 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request enabled
Transmit Interrupt Enable
0 Transmit data empty interrupt (TXI) requests disabled
1 Transmit data empty interrupt (TXI) requests enabled
TDR2—Transmit Data Register 2
Bit
:
7
6
H'FF8B SCI2, Smart Card Interface 2
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
Read/Write : _R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores data for serial transmission
Rev.6.00 Oct.28.2004 page 931 of 1016
REJ09B0138-0600H