Z80 Datasheet, PDF (94/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 11. Contents of Counters After DMA Stops Because of End-of-Block (Transfer
Operations)
Class
Sequential
Transfer
Search Only or
Simultaneous
Transfer/Search
Mode
Byte
Burst
Continuous
Byte
Burst
Burst
Continuous
Continuous
Programmed
Block Length
N
N
N
N
N
N
N+1
N+1
Bytes Transferred
Source Port
Destination Port
At Stop
Byte Counter Address Counter* Address Counter*
N+1
N+1
N+1
N+1
N+1
N+2**
N+1
N+2**
N
N
N
N
N+1
N+1 **
N+1
N+1 **
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+2)**
As±(N+1)
As±(N+2)**
As±(N)
As±(N)
As±(N)
***
***
***
***
***
Notes:
* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the first
address for transfer purposes.
** Occurs only in 2-cycle (variable timing) simultaneous transfers when the Ready line is still active at the end
of the N + 1 byte transfer.
*** Simultaneous transfers cannot have both ports variable. This class of operation is programmed as a DMA
search-only operation, with variable addresses ascribed to the programmed source port. What the DMA senses
is the source port may be either the real source or destination, as determined by external hardware. See “The
actual number of bytes transferred is one more than specified by the block length.
* These entries are
necessary only in the case of a fixed destination address.” on page 129.
Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/
Search Operations)
Class
Mode
Match Occurs Bytes Transferred At Stop
On This Byte If Transferring
Byte Counter
Sequential
Byte
M
M
Transfer
Burst
M
M
Continuous M
M+
Search Only or Byte
M
M
Simultaneous
Transfer Search
Burst
M
M+1
Burst
M
M**
Continuous M
M+1
M-1
M-1
M-1
M
M+1
M-1**
M+1
Source Port
Destination Port
Address Counter* Address Counter
As±(M)
As±(M)
As±(M)
As±(M)
As±(M+1)
As±(M**
As±(M+1)
As±(M-1)
As±(M-)
As±(M -)
***
***
***
***
UM008101-0601
Direct Memory Access