Z80 Datasheet, PDF (184/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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RDY
BUSREQ
BAI
A15–A0
MREQ
RD
D7–D0
Figure 72. RDY Line in Continuous Mode
Variable Cycle and Edge Timing
The Z80 DMA’s operation-cycle length, without Wait states for the source
(read) port and destination (write) port, can be independently programmed.
This variable-cycle feature allows read or write cycles consisting of two,
three, or four clock cycles, more if Wait cycles are inserted, increasing or
decreasing the pulse widths of all signals generated by the DMA. In addi-
tion, the trailing edges of the IORQ, MREQ, RD, and WR signals can be
independently terminated one-half cycle early. See Figure 73 .
UM008101-0601
Direct Memory Access