Z80 Datasheet, PDF (158/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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The event sequences for SIO-DMA transfers are described in Table 17 and
Table 18.
Table 17. Receive Event Sequence
Event
Inter-event delay
(clock periods)
SIO receives last bit of character 10-13
SIO RDY becomes active
2
DMA asserts BUSREQ
1-5
Current CPU machine cycle ends 1
CPU asserts BUSACK
4
latency
latency
latency
latency, bus occupancy
latency, bus occupancy
DMA I/O read cycle begins
4
DMA memory write cycle begins 2
DMA terminates BUSREQ
1
DMA memory write cycle ends 1
latency, bus occupancy
bus occupancy
bus occupancy
bus occupancy
CPU terminates BUSACK and 1
regains control of bus
bus occupancy
Note: Latency (delay from reception of final data bit to reading of received data) is 22 to
29 clock periods. The system bus is occupied by the DMA for 13 clock periods per byte
transferred.
Table 18. Transmit Event Sequence
Event
Inter-event delay
(clock periods)
SIO transmits last bit of character 5-6
SIO RDY becomes true
2
DMA asserts BUSREQ
1-5
Current CPU machine cycle ends 1
CPU asserts BUSACK
4
DMA memory read cycle begins 3
latency
latency
latency
latency, bus occupancy
latency, bus occupancy
latency, bus occupancy
UM008101-0601
Direct Memory Access