Z80 Datasheet, PDF (186/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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and any functions created from it by external logic in simultaneous transfer
operations (such as IOWR and IORD), remain active during an inactive
RDY line before stopping on end-of-block or byte match.
Interrupts
Timings for interrupt acknowledge and return from interrupt are the same
as timings for these in other Z80 peripherals. Figure 74 illustrates this
timing. The interrupt signal INT is sampled by the CPU on the rising edge
of the final clock cycle of any instruction. The signal is not accepted if the
internal CPU software-controlled interrupt-enable flip-flop is not set or if
the BUSREQ signal is active. When the INT signal is accepted, a special
M1 cycle is generated.
T₁
T₂
T₃
T₄
CLK
CE/WAIT
(3-Cycle and
4-Cycle Memory
Operations)
CE/WAIT
(4-Cycle I/O
Operations)
Figure 74. WAIT Line Sampling in Variable-Cycle Timing
During this special M1 cycle, the IORQ signal becomes simultaneously
active (instead of the normal MREQ), indicating that the interrupting
device can place its 8-bit vector on the data bus. Two wait states are auto-
matically added to this cycle. These states are added so that a ripple-priority
interrupt scheme can be easily implemented. The two wait states allow time
for the ripple signals to stabilize and identify what I/O device must respond.
Refer to the Z80 CPU User’s Manual for more details.
UM008101-0601
Direct Memory Access