Z80 Datasheet, PDF (269/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
249
All interrupts may be disabled for operation in a Polled mode or to avoid
interrupts at inappropriate tunes during the execution of a program.
Synchronous Receive
Initialization
The system program initiates the Synchronous Receive operation with the
following parameters: odd or even parity, 8-bit or 16-bit sync characters, x1
clock mode, CRC polynomial, receive character length, and more. Sync
characters must be loaded to registers WR6 and WR7. The receivers can be
enabled only after all receive parameters are set. WR4 parameters must be
issued before WR1, WR3, WR5, WR6, and WR7 parameters or commands.
After these condititons are met, the receiver is in the Hunt phase. It remains in
this phase until character synchronization is achieved. Under program
control, all the leading sync characters of the message can be inhibited from
loading the receive buffers by setting the Sync Character Load Inhibit bit in
WR3.
Data Transfer and Status Monitoring
After character synchronization is achieved, the assembled characters are
transferred to the receive data FIFO. The following four interrupt modes are
available to transfer the data and its associated status to the CPU.
No Interrupts Enabled
This mode is used for a purely polled operation or for off-line conditions.
Interrupt On First Character Only
This mode is normally used to start a polling loop or a Block Transfer
instruction using WAIT/READY to synchronize the CPU or the DMA
device to the incoming data rate. In this mode, the Z80 SIO interrupts on
the first character and thereafter interrupts only if Special Receive condi-
UM008101-0601
Serial Input/Output