Z80 Datasheet, PDF (207/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D₂ 1
D₇ 2
D₆ 3
CE 4
40 D₃
39 D₄
38 D₅
37 M1
C/D 5
36 IORQ
B/A 6
35 RD
PA₇ 7
34 PB₇
PA₆ 8
33 PB₆
PA₅ 9
32 PB₅
PA₄ 10 Z80 31 PB₄
GND 11 PIO 30 PB₃
PA₃ 12
29 PB₂
PA₂ 13
28 PB₁
PA₁ 14
27 PB₀
PA₀ 15
26 +5V
ASTB 16
25 CLK
BSTB 17
24 IEI
ARDY 18
23 INT
D₀ 19
D₁ 20
22 IEO
21 BRDY
Figure 6. 40-Pin DIP Pin Assignments
PROGRAMMING THE PIO
Reset
The Z80 PIO automatically enters a reset state when power is applied. The
reset state performs the following functions:
1. Both port mask registers are reset to inhibit all port data bits.
2. Port data bus lines are set to a high-impedance state and the Ready
handshake signals are inactive (Low). Mode 1 is automatically selected.
3. The vector address registers are not reset.
4. Both port interrupt enable flip-flops are reset.
5. Both port output registers are reset.
UM008101-0601
Parallel Input/Output