Z80 Datasheet, PDF (289/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
269
Table 10. SDLC Receive Mode (Continued)
Function
WR4
WR0
WR5
WR0
WR3
WR0
WR6
WR0
WR7
WR0
WR1
WR0
WR3
Typical Program Steps
Comments
Parity information, Sync Mode, SDLC
Mode, X1 Clock Mode
Pointer 5, Reset External/Status
Interrupts
SDLC-CRC, Data Terminal Ready
Pointer 3
Receive CRC Enable, enter Hunt Mode, Auto Enables enables the receiver to
Auto Enables, Receive Character Length, accept data only after MB becomes
Address Search Mode
active. Address Search Mode Enables
Pointer 6
SIO to match the message address
with the programmed address or the
global address.
Secondary Address Field
Pointer 7
This address is compared to the
message address in an SDLC Poll
operation.
SDLC Flag 0111 1110
This flag detects the start and end-of-
Pointer 1, Reset External/Status
frame in an SDLC Operation. In this
Interrupts
Interrupt Mode, only the address field
Status Affects Vector, External Interrupt
Enable, Receive Interrupt on first
character only.
(1 character only) is transferred to the
CPU. All subsequent fields (control,
information, and more.) are
transferred on a DMA basis. Status
Affects Vector in Channel B only.
Pointer 3, Enable Interrupt on next
Receive Character
This flag provides simple loop-back
entry point for next transaction.
Receive Enable, Receive CRC Enable,
enter Hunt Mode, Auto Enables,
Receiver Character Length, Address
Search Mode
WR3 reissued to enable receiver.
UM008101-0601
Serial Input/Output