Z80 Datasheet, PDF (228/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

< %27 2GTKRJGTCNU
7UGT /CPWCN
208
• TTL-Compatible Inputs and Outputs
• Two Independent Full-Duplex Channels
• Data Rates in Synchronous or Isosynchronous Modes:
– 0-800K Bits/Second with 4 MHz System Clock Rate
– 0-1.2M Bits/Second with 6 MHz System Clock Rate
– 0-2.5M Bits/Second with 10 MHz System Clock Rate
• Receiver Data Registers Quadruply Buffered; Transmitter Doubly
Buffered
• Asynchronous Features:
– 5, 6, 7, or 8 Bits per Character
– 1, 1 1/2, or 2 Stop Bits
– Even, Odd, or No Parity
– x1, x16, x32, and x64 Clock Modes
– Break Generation and Detection
– Parity, Overrun, and Framing Error Detection
• Binary Synchronous Features:
– Internal or External Character Synchronization
– One or Two Sync Characters in Separate Registers
– Automatic Sync Character Insertion
– CRC Generation and Checking
• HDLC and IBM SDLC Features:
– Abort Sequence Generation and Detection
– Automatic Zero Insertion and Deletion
– Automatic Flag insertion Between Messages
– Address Field Recognition
– 1-Field Residue Handling
– Valid Receive Messages Protected from Overrun
UM008101-0601
Serial Input/Output