Z80 Datasheet, PDF (124/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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• Reinitialize Ports A and B to standard Z80 cycle timing (see WR1
and WR2)
At power-up, one reset command is sent to the DMA prior to the initial-
ization program. When aborting an operation sequence, sending six reset
commands guarantees resetting (this is because WR4 has five associated
registers that can potentially be pointed to).
The RESET command does not perform a complete DMA reset. For
example, it does not reset the read sequence, which is set by the INITIATE
READ SEQUENCE command.
Reset Port A Timing (C7)
Resets the Port A variable timing byte in WR1 to standard Z80 timing. The
RESET command also perform this function.
Reset Port B Timing (CB)
Resets the Port B variable timing byte in WR2 as described in Reset Port A
Timing (C7).
Load (CF)
This command must be used to write new addresses to the address registers
(WR0 and/or WR4) or to restart an operation (except Auto Restart) at the
same addresses. It loads the contents of both starting-address registers to
their associated address counters (Figure 30). It also clears the byte counter
associated with the block-length register, and it unforces an internal Force
Ready condition. The starting addresses must be written in WR0 and/or
WR4 before the LOAD command is written, if they are to differ from the
previous starting addresses.
Only the source-port address counter is immediately loaded. The desti-
nation-port address counter (if used) is loaded during the first count of the
destination-port address. If the destination-port address is fixed, this indi-
UM008101-0601
Direct Memory Access