Z80 Datasheet, PDF (105/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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• Reset and disable DMA interrupts
– Enable DMA interrupts
– Disable DMA interrupts
• Load new starting addresses and block length
– Continue prior address counting
– Clear block length counter
• Force the Ready condition
• Read the status byte
– Initiate a status-register read sequence
– Clear status
Interrupt service routines on a Z80 CPU always end with a Return From
Interrupt (RETI or hex ED4D) instruction, which is now explained.
+5V
Interrupt Condition (Active RDY)
Enable after RETI
Reset and Disable Interrupts
D-FLIP-FLOP
D
O
CY IOR
R
Disable DMA
*NOTE: This latch is only set when the Interrupt-On-Ready option is selected.
Figure 36. Interrupt On Ready (IOR) Latch
Return From Interrupt
At the end of an interrupt service routine, the Z80 CPU executes a return-
from-interrupt (RETI or hex ED4D) instruction. This returns the CPU from
the interrupt service routine.
The DMA also simultaneously decodes the RETI instruction, which it
recognizes on the data bus as an instruction (occurring when the DMA’s
M1 input is Low). This causes at least one, and possibly two, events within
the DMA:
UM008101-0601
Direct Memory Access