Z80 Datasheet, PDF (123/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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D7 D6 D5 D4 D3 D2 D1 D0
10
0 1 0 Base Register Byte
0 = Ready Active Low
1 = Ready Active High
0 = CE Only
1 = CE/WAIT Only
0 = Stop on End-of-Block
1 = Auto Restart on End-of-Block
Figure 45. Write Register 5 Group
Write Register 6 Group
The base register byte for this group has bits 7, 1, and 0 set to one, which
Figure 46 depicts. The remaining bits specify 16 commands that are
commonly used after DMA initialization (for example, within CPU
interrupt service routines), and to point to a read mask for the read registers.
Each of these commands, except the ENABLE DMA command, disables
the DMA. Therefore, the ENABLE DMA command must be the last
command written before DMA bus requests can begin.
Reset (C3)
This command is used at power-up and when aborting a program sequence
to do the following:
• Disable interrupt and bus-request logic
• Reset interrupt latches
• Unforce a FORCE READY condition
• Reset the Auto Repeat function (see WR5)
• Reset the Wait function (See WR5)
UM008101-0601
Direct Memory Access