Z80 Datasheet, PDF (42/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CTC TIMING
Overview
This section describes the timing relationships of the relevant CTC pins for
the following types of operation:
• Writing a word to the CTC
• Reading a word from the CTC
• Counting and timing
A timing diagram, Figure 12, relating to interrupt servicing is found in
“Interrupt Acknowledge Cycle” on page 28.
CTC Write Cycle
Figure 9 illustrates the timing associated with the CTC Write cycle. This
sequence is applicable to loading a channel control word, an interrupt
vector, or a time constant data word.
In the sequence shown, during clock cycle T1, the Z80 CPU prepares for
the Write cycle with a false (High) signal at CTC input pin RD (Read).
Because the CTC has no separate Write signal input, it generates its own
input internally from the false RD input. During clock cycle T2, the Z80
CPU initiates the Write cycle with true (Low) signals at CTC input pins
IORQ (I/O Request) and CE (Chip Enable). (See Note below.) A 2-bit
binary code appears at CTC inputs CS1 and CS0 (Channel Select 1 and 0),
specifying which of the four CTC channels is being written to. At this time,
a channel control, interrupt vector, or time constant data word may be
loaded to the appropriate CTC internal register in synchronization with the
rising edge beginning clock cycle T3.
Note: M1 must be false to distinguish the cycle from an interrupt
acknowledge.
UM008101-0601
Counter/Timer Channels