Z80 Datasheet, PDF (294/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

< %27 2GTKRJGTCNU
7UGT /CPWCN
274
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0 Register 0
0
0
1 Register 1
0
1
0 Register 2
0
1
1 ^{Register 3}
1
0
0 Register 4
1
0
1 Register 5
1
1
0 Register 6
1
1
1 Register 7
0
0
0 Null Code
0
0
1 Send Abort (SDLC)
0
1
0 Reset Ext/Status Interrupts
0
1
1 Channel Reset
1
0
0 Enable INT on Next Ax Character
1
0
1 Reset TxINT Pending
1
1
0 Error Reset
1
1
1 Return from INT (CH-A Only)
0
0 Null Code
0
1 Reset Rx CRC Checker
1
0 Reset Tx CRC Generator
1
1 Reset Tx Underrun/EOM Latch
Figure 114. Write Register 0
Pointer Bits (D2-D0)
Bits D2-D0 are pointer bits that determine which write register the next
byte writes to or which read register the next byte reads from. The first byte
written to each channel after a reset (either by a Reset command or by the
external reset input) goes to WR0. Following a read or write to any register
(except WR0), the pointer points to WR0
Command Bits (D5-D3)
Three bits, D5-D3, are encoded to issue the seven basic Z80 SIO
commands (Table 13).
UM008101-0601
Serial Input/Output