Z80 Datasheet, PDF (291/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
271
Table 10. SDLC Receive Mode (Continued)
Function
Termination
Typical Program Steps
Comments
When End Of Frame Interrupt occurs, the Detection of End-of-frame (flag)
CPU performs
causes Interrupt and deactivates the
the following:
Wait/Ready function. Residue codes
• Exits DMA Mode (disables Wait/
Ready)
• Transfers RR1 to the CPU
• Checks the CRC error bit status and
residue codes
indicate the bit structure of the last
two bytes of the message that were
transferred to memory under DMA.
'error Reset' is issued to clear the
special condition. Abort Sequence is
detected when seven or more 1s occur
• Updates NR count
in the data stream.
• Issues Error Reset Command to SIO
When Abort Sequence Detected Interrupt
occurs, the CPU performs the following:
• Transfers RR0 to the CPU
• Exits DMA Mode
• Issues the Reset External Status
Interrupt Command to the SIO
• Enters the Idle Mode
When the second Abort Sequence
Interrupt occurs, the CPU performs the
following:
• Issues the Reset External Status
Interrupt Command to the SIO
CPU is waiting for Abort Sequence to
terminate. Termination clears the
Break/Abort status bit and causes
interrupt. at this point, the program
proceeds to terminate this message.
Redefine Interrupt Modes, Sync Mode
and SDLC Modes, Disable Receive
Mode
UM008101-0601
Serial Input/Output