Z80 Datasheet, PDF (77/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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The match byte written into the DMA is masked with another byte so that
only certain bits within the match byte can be compared with the corre-
sponding bits in the data bytes being searched.
Interrupts
The DMA can be programmed to interrupt the CPU on three conditions:
• Interrupt on Ready
• Interrupt on Byte Match
• Interrupt on End-of-Block
The first condition (I/O-port Ready line becoming active) causes an
interrupt before the DMA requests the bus. The other two conditions
cause the DMA to interrupt the CPU after the DMA stops (releases the
bus). Stopping the DMA on byte match or end-of-block is separately
programmed.
Any of these conditions (Ready line becoming active, byte match, or end-
of-block) causes a readable status bit to be set. In addition, when an
interrupt on any of these conditions is programmed, an interrupt-pending
status bit is also set, and each type of interrupt can optionally alter the
DMAs interrupt vector.
The DMA shares the Z80 Family’s versatile interrupt scheme, which
provides fast interrupt service in real-time applications. In a Z80 CPU
environment where the CPU is using its Mode 2 interrupts, the DMA
passes its internally modifiable 8-bit interrupt vector to the CPU, which
attaches an additional eight bits to form the memory address of the
interrupt routine table. This table contains the address of the beginning of
the interrupt routine. In this process, CPU control is transferred to the
interrupt routine, so that the next instruction executed after an interrupt
acknowledge is the first instruction of the interrupt routine.
UM008101-0601
Direct Memory Access