Z80 Datasheet, PDF (246/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CPU I/O
I/O Data Buffer
Internal Data Bus
RxDA
RxCA
Receive
Error
FIFO
Receive
Error
FIFO
WR7
SYNC
Register
WR6
SYNC
Register
Transmit
Data
Hunt Mode (BISYNC)
Receive
Error
Logic
1-Bit
Delay
SYNC
Register
and Zero
Delete
ASYNC Data
Receive
Clock
Logic
3 Bits
Receive
S.R.
(8 Bits)
SYNC-
CRC
CRC Delay
Register
(8 Bits)
SDLC-CRC
CRC
Checker CRC Result
20-Bit Transmit Shift Register
Start Bit
ASYNC Data
SYNC Data
SDLC Data
Zero
Insert
SYNC-CRC
(5 Bits)
Transmit
Multiplexer
and
2-Bit
Delay
SDLC-CRC
CRC
Generator
Transmit
Clock Logic
TxDA
TxCA
Figure 109. Transmit and Receive Data Path
Functional Description
The functional capabilities of the Z80 SIO are described in two ways: as a
data communications device, and as a Z80 family peripheral.
As a data communications device, The S80 SIO transmits and receives
serial data, and meets the requirements of various data communications
protocols. As a Z80 family peripheral, it interacts with the Z80 CPU and
other Z80 peripheral, circuits, and shares their data, address and control
UM008101-0601
Serial Input/Output