Z80 Datasheet, PDF (100/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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End-of-Block
or Byte Match
DMA
BUSREQ
*
BAI
CPU
BUSREQ
BUSACK
DMA Releases
Bus and
Interrupts CPU
CPU Acknowledges
Interrupt
INT
INT *
M1
IORQ
M1
*
IORQ
DMA Passes
Interrupt Vector
*
to CPU
CPU Executes
Interrupt Service
Routine
MEMORY
DMA Requests
Bus Again
BUSREQ
BAI
BUSREQ
BUSACK
*Bus Master
Figure 32. Z80 Interrupt Sequence
Interrupt Vectors
The Z80 CPU interrupt acknowledge cycle causes the DMA to put its 8-bit
interrupt vector on the data bus (Figure 33a). This vector is read by the
UM008101-0601
Direct Memory Access