Z80 Datasheet, PDF (189/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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REGISTER BIT FUNCTIONS
Write Register Bit Functions
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 0 Do not use
0 1 = Transfer
1 0 = Search
1 1 = Search/Transfer
0 = Port B → Port A
0 = Port A → Port B
Port A Starting Address
(Low Byte)
Port A Starting Address
(High Byte)
Block Length
(Low Byte)
Block Length
(High Byte)
Figure 76. Write Register 0 Group
D7 D6 D5 D4 D3 D2 D1 D0
0
1 0 0 Base Register Byte
0 = Port A is Memory
0 = Port A is I/O
0 0 = Port A Address Decrements
0 1 = Port A Address Increments
1
1
0
1
= Port A Address Fixed
00
Port A Variable
Timing Byte
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
0 0 = Cycle Length = 4
0 1 = Cycle Length = 3
1 0 = Cycle Length = 2
1 1 = Do Not Use
MREQ Ends 1/2 Cycle Early = 0 0 = IORQ Ends 1/2 Cycle Early
Figure 77. Write Register 1 Group
UM008101-0601
Direct Memory Access