Z80 Datasheet, PDF (233/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
213
they are inputs similar to CTS and DCD. In this mode, the transitions on
these lines affect the state of the Sync/Hunt status bits in RR0. In the
External Sync mode, these lines also act as inputs. When external synchro-
nization is achieved, SYNC must be driven Low on the second rising edge
of RxC after that rising edge of RxC on which the last bit of the sync char-
acter was received. In other logic must wait for two full Receive Clock
cycles to activate the SYNC input. When SYNC is forced Low, keep it Low
until the CPU notifies the external sync logic that synchronization has been
lost or that a new message is about to start. Character assembly begins on
the rising edge of RxC that immediately precedes the falling edge of SYNC
in the External Sync mode.
In the Internal Synchronization mode (Monosync and Bisync), these pins
function as outputs that are active during the part of the receive clock (RxC)
cycle in which sync characters are recognized. The sync condition is not
latched, therefore, these outputs are active each time a sync pattern is recog-
nized, regardless of character boundaries.
Bonding Options
The constraints of a 40-pin package make it impossible to bring out the
Receive Clock, Transmit Clock, Data Terminal Ready, and Sync signals for
both channels. Therefore, Channel B must sacrifice a signal or have two
signals bonded together. Because user requirements vary, three bonding
options are offered:
• Z80 SIO/0 contains all four signals, but TxCB and RxCD are bonded
together (Figure 101).
• Z80 SIO/1 sacrifices DTRB and keeps TxCB, RxCD and SYNCB
(Figure 103).
• Z80 SIO/2 sacrifices SYNCB and keeps TxCB, RxCB and DTRB
(Figure 105).
• The 44-pin package version SIO/3 (QFP) and SIO/4 (PLCC) have all
signals (Figure 107 and Figure 108).
UM008101-0601
Serial Input/Output