Z80 Datasheet, PDF (82/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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states to be inserted in the DMA’s operation cycles, thereby slowing the
DMA to a speed that matches the memory or I/O device. The Applications
chapter contains a description of how the CE and WAIT inputs can be
multiplexed by the CPU’s BUSACK line.
CLK
System Clock (input). This pin is standard Z80 single-phase clock at 2.8
MHz (Z80 DMA) or 4.0 MHz (Z80A DMA). For slower system clocks, a
TTL gate with a pull-up resistor may be adequate to meet the timing and
voltage level specifications. For higher speed systems, use a clock driver
with an active pull-up to meet the VIH specification and rise time require-
ments. There should always be a resistive pull-up to the power supply (10
Kohms maximum), ensuring correct power at DMA reset.
D7-D0
System Data Bus (bidirectional, tristate). These pins transfer control bytes
from the CPU, status byes from the DMA, and data from memory or I/O
peripherals. Data transfers or searches by the DMA occur only when the
DMA controls both this bus and the address bus. When the CPU controls
these buses, it can write or read DMA control or status bytes.
IEI
Interrupt Enable In (input, active High). This line, combined with the IEO,
form a priority daisy-chain when there is more than one interrupting device.
A High on this line indicates that no other device of higher priority is inter-
rupting, thereby allowing this DMA to interrupt.
IEO
Interrupt Enable Out (output, active High). IEO is High only when IEI is
High and this DMA is not requesting an interrupt. Therefore, this signal
blocks lower priority devices from interrupting while a higher priority
device is being serviced by its CPU interrupt service routine. Unlike
devices in a bus-request daisy-chain, devices in an interrupt daisy-chain can
UM008101-0601
Direct Memory Access