Z80 Datasheet, PDF (243/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
223
Table 1. Write Register Functions
Bit
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Function
Register pointers, CRC initialize, initialization commands for the
various modes and more
Transmit/Receive interrupt and data transfer mode definition
Interrupt vector (Channel B only)
Receive parameters and controls
Transmit/Receive miscellaneous parameters and modes
Transmit parameters and controls
Sync character or SDLC address field
Sync character or SDLC flag
Table 2. Read Register Functions
Bit Function
RR0 Transmit/Receive buffer status, interrupt status, and external status
RR1 Special Receive Condition status
RR2 Modified interrupt vector (Channel B only)
Data Path
The transmit and receive data path for each channel is depicted in
Figure 109. The receiver contains three 8-bit buffer registers in a FIFO
arrangement (to provide a 3-byte delay) in addition to the 8-bit receive shift
register. This arrangement creates additional time for the CPU to service an
interrupt at the beginning of a block of high-speed data. The receive error
FIFO stores parity and framing errors and other types of status information
for each of the three bytes in the receive data FIFO.
Incoming data is routed through one of several paths depending on the
mode and character length. In the Asynchronous mode, serial data is
UM008101-0601
Serial Input/Output