Z80 Datasheet, PDF (304/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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284
D7 D6 D5 D4 D3 D2 D1 D0
0
0 Rx 5 Bits/Character
0
1 Rx 7 Bits/Character
1
0 Rx 6 Bits/Character
1
1 Rx 8 Bits/Character
Figure 117. Write Register 3
Rx Enable
SYNC Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Phase
Auto Enables
Receiver Bits/Characters 1 and 0 (D7 and D6)
Used together, these bits determine the number of serial receive bits
assembled to form a character. Both bits may be changed during the time
that a character is being assembled, but they must be changed before the
currently programmed number of bits is reached.
Table 21. Serial Bits/Character
D7
D6
0
0
0
1
1
0
1
1
Bits/Character
5
7
6
8
Write Register 4
WR4 contains the control bits that affect both the receiver and transmitter.
In the transmit and receive initialization routine, these bits should be set
before issuing WR1, WR3, WR5, WR6, and WR7.
UM008101-0601
Serial Input/Output