Z80 Datasheet, PDF (288/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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SDLC Receive Termination
If enabled, a special vector is generated when the closing flag is received.
This signals that the byte with the End-of-Frame bit set has been received.
In addition to the results of the CRC check, RR1 has three bits of Residue
code valid at this time. When the number of bits in the I-Field is not an inte-
gral multiple of the character length used, these bits indicate the boundary
between the CRC check bits and the I-Field bits. For a detailed description
of the meaning of these bits, see the description of the residue codes in RR1
in “Z80 SIO Programming.”
Any frame can be prematurely aborted by an Abort sequence. Aborts are
detected if seven or more 1s occur, causing an External/Status interrupt (if
enabled) with the Break/Abort bit in RR0 set. After the Reset External/
Status interrupts command has been issued, a second interrupt occurs when
the continuous 1s condition has been cleared. This can be used to distin-
guish between the Abort and Idle line conditions.
Unlike the synchronous mode, CRC calculation in SDLC does not have an
8-bit delay because all the characters are included in CRC calculation.
When the second CRC character is loaded to the receive buffer, CRC calcu-
lation is complete.
Table 10 lists steps employed to implement a half-duplex SDLC receive
mode. The complete set of command and status bit definitions is provided
in the next section.
Table 10. SDLC Receive Mode
Function
Typical Program Steps
Register Information loaded:
Initialize WR0 Channel 2
WR0 Pointer 2
WR2 Interrupt Vector
WR0 Pointer 4
Comments
Reset SIO
Channel B only
UM008101-0601
Serial Input/Output