Z80 Datasheet, PDF (290/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

< %27 2GTKRJGTCNU
7UGT /CPWCN
270
Table 10. SDLC Receive Mode (Continued)
Function
Typical Program Steps
Comments
Idle Mode
Execute Halt Instruction or some other
program
SDLC Receive Mode is fully
initialized and SIO is waiting for the
opening flag followed by a matching
address field to interrupt the CPU.
Data Transfer and When Interrupt On First Character
Status
occurs, the CPU
Monitoring
performs the following:
• Transfers Data Byte (address byte) to
CPU
• Detects And Sets appropriate Flag for
Extended Address Field
During the Hunt Phase, the SIO
interrupts when the programmed
address matches the message address.
The CPU establishes the DMA Mode
and all subsequent data characters are
transferred by the DMA controller to
memory.
• Updates pointers and parameters
• Enables DMA Controller
• Enables Wait/Ready function in SIO
• Returns from Interrupt
When the Ready Output becomes active, During the DMA operation, the SIO
the DMA Controller performs the
monitors the DCD Input and the Abort
following:
sequence in the data stream to
• Transfers the Data Byte to memory
• Updates the pointers
interrupt the CPU with external status
error. The special receive condition
interrupt is caused by the Receive
Overrun Error.
UM008101-0601
Serial Input/Output