Z80 Datasheet, PDF (27/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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According to Z80 system convention, all addresses in the interrupt service
routine table place their low-order byte in an even location in memory, and
their high-order byte in the next highest location in memory. This location is
always odd so that the least-significant bit of any interrupt vector is always
even. Therefore, the least-significant bit of any interrupt vector always zero.
The RETI instruction is used at the end of an Interrupt Service Routine to
initialize the Daisy Chain Enable line IEO for control of nested priority
interrupt handling. The CTC monitors the system data bus and decodes this
instruction when it occurs. Therefore, the CTC channel control logic knows
when the CPU has completed servicing an interrupt.
CTC PIN DESCRIPTION
Pin Functions
Diagrams of the Z80 CTC Pin Configuration and Z80 CTC Package
Configuration are illustrated in Figure 4 through Figure 7, respectively.
This section describes the function of each pin.
UM008101-0601
Counter/Timer Channels