Z80 Datasheet, PDF (249/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
229
interrupt is also caused by a Transmit Underrun condition or by the detec-
tion of a Break (Asynchronous mode) or Abort (SDLC mode) sequence in
the data stream. The interrupt caused by the Break/Abort sequence has a
special feature that allows the Z80 SIO to interrupt when the Break/Abort
sequence is detected or terminated. This feature facilitates the proper termi-
nation of the current message, correct initialization of the next message,
and the accurate timing of the Break/Abort condition in external logic.
CPU/DMA Block Transfer
The Z80 SIO provides a Block Transfer mode to accommodate CPU block
transfer functions and DMA controllers (Z80-DMA or other designs). The
Block Transfer mode uses the WAIT/READY output in conjunction with
the Wait/Ready bits of Write Register 1. The WAIT/READY output can be
defined under software control as a WAIT line in the CPU Block Transfer
mode or as a READY line in the DMA Block Transfer mode.
To a DMA controller, the Z80 SIO READY output indicates that the Z80
SIO is ready to transfer data to or from memory. To the CPU, the WAIT
output indicates that the Z80 SIO is not ready to transfer data, thereby
requesting the CPU to extend the I/O cycle. The programming of bits 5, 6,
and 7 of Write Register 1 and the logic states of the WAIT/READY line are
defined in “Write Register 1” on page 279.
Data Communications Capabilities
In addition to the I/O capabilities previously discussed, the Z80 SIO
provides two independent full-duplex channels as well as Asynchronous,
Synchronous, and SDLC (HDLG) operational modes. These modes facili-
tate the implementation of commonly used data communications protocols.
The specific features of these modes are described in the following
sections. To preserve the independence and completeness of each section,
some information common to all modes is repeated.
UM008101-0601
Serial Input/Output