Z80 Datasheet, PDF (75/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 8. Maximum Transfer and Search Speeds (Burst and Continuous
Modes)
Action
DMA Simultaneous Transfer
DMA Search Only
DMA Simultaneous Transfer/Search
DMA Sequential Transfer
DMA Sequential Transfer/Search
CPU Block Transfer Instruction
Z80
(2.4 MHz)
1.25
MB/s
Z80Z
(4.0 MHz)
2.0
MB/s
0.625
MB/s
0.125
MB/s
1.0
MB/s
0.200
MB/s
Table 9. Reduction in Z80 CPU Throughput per Kbaud
(Byte Mode Transfers)
Action
DMA Sequential Transfer
DMA Sequential Transfer/Search
CPU Interrupt Driven Transfer
Z80
(2.4 MHz)
0.085%
0.340%
Z80Z
(4.0 MHz)
0.041%
0.213%
Address Generation
Two 26-bit addresses are generated by the DMA for every transfer oper-
ation: one address for the source port and another for the destination port.
The two addresses are multiplexed onto the address bus, according to
whether the DMA is reading the source or writing to the destination.
The two ports are arbitrarily named Port A and Port B. Both A and B can be
either source or destination, either memory or I/O, and have fixed or
variable addresses.
UM008101-0601
Direct Memory Access