Z80 Datasheet, PDF (204/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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BRDY
Register B Ready (output, active High). The meaning of this signal is
similar to that of A Ready with the following exception: In the Port A bidi-
rectional mode, this signal is High when the Port A input register is empty
and ready to accept data from the peripheral device.
CPU
Data
BUS
D0
19
D1
20
A2
1
D3
40
D4
39
D5
38
D6
3
D7
2
Port B/A SEL
6
Control/Data SEL
5
PIO
Control
Chip Enable
4
M1
37
IORQ
36
RD
35
+5V
26
GND
11
Φ
25
Interrupt
Control
INT
23
INT Enable in
24
INT Enable out
22
Z80 – PIO
15
A0
14
A1
13
A2
12
A3
10
A4
9
A5
8
A6
7
A7
Port A
I/O
18
ARDY
16
ASTB
27
B0
28
B1
29
B2
30
B3
31
B4
32
B5
33
B6
34
B7
Port B
I/O
21
BRDY
17
BSTB
Figure 3. PIO Pin Functions
UM008101-0601
Parallel Input/Output