Z80 Datasheet, PDF (278/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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information field may be sent to the Z80 SIO using the Transmit Interrupt
mode. The Z80 SIO transmits the Frame Check sequence using the
Transmit Underrun feature.
When the transmitter is first enabled, it is already empty and cannot then
become empty. Therefore, no Transmit Buffer Empty interrupts can occur
until after the first data character is written.
Table 8. Contents of Write Registers 3, 4, and 5 in SDLC Modes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
WR 00 = Rx 5 Bits Char
3 10 = Rx 6 Bits Char
01 = Rx 7 Bits Char
11 = Rx 8 Bits Char
Auto
Enables
Enter Hunt Rx CRC
Mode (if Enable
incoming
data not
needed)
Address
Search
Mode
WR 0
0
4
1
0
0
0
Selects Selects
SDLC SDLC
Mode Mode
WR DTR
5
00 = Tx 5 Bits (or less) 0
Char
10 = Tx 6 Bits Char
01 = Tx 7 Bits Char
11 = Tx 8 Bits Char
Tx Enable 0
Selects
SDLC
CRC
Bit 1
0
0
RTS
Bit 0
Rx
Enable
0
Tx CRC
Enable
Data Transfer Using WAIT/READY
When the Wait/Ready function is selected, WAIT communicates to the
CPU that the Z80 SIO is not ready to accept the data and that the CPU must
extend the I/O cycle. To a DMA controller, READY communicates that the
transmitter buffer is empty and that the Z80 SIO is ready to accept the next
character. If the data character is not loaded to the Z80 SIO by the time the
transmit shift register is empty, the Z80 SIO enters the Transmit Underrun
condition. Address, control, and information fields may be transferred to
UM008101-0601
Serial Input/Output