Z80 Datasheet, PDF (26/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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A CTC channel may be programmed to request an interrupt every time its
down-counter reaches a count of zero. However, using this feature requires
that the CPU be in INTERRUPT Mode 2. After the interrupt request, the
CPU sends out an interrupt acknowledge. The CTC’s interrupt control
logic determines the highest-priority channel requesting an interrupt. If
the CTC’s IEI input is active, indicating that it has priority within the
system daisy-chain, it places an 8-bit interrupt vector on the system data
bus as follows:
1. The high order five bits of this vector were written to the CTC earlier
as part of the CTC initial programming process.
2. The next two bits are provided by the CTC’s interrupt control logic as a
binary code corresponding to the highest-priority channel requesting an
interrupt.
3. The low-order bit of the vector is always zero according to a
convention (Figure 3).
This interrupt vector is used to form a pointer to a location in memory
where the address of the interrupt service routine is stored in a table. The
vector represents the least-significant eight bits. The CPU reads the
contents of the I register to provide the most-significant eight bits of the
16-bit pointer. The address pointed to in memory contains the low-order
byte and the next highest address contains the high-order byte of an
address, which in turn contains the first Op Code of the interrupt service
routine. Thus, in Mode 2, a single 8-bit vector stored in an interrupting
CTC can result in an indirect call to any memory location (Figure 3).
Z80 16-Bit Pointer (Interrupt Starting Address)
1 Reg
Contents
7 Bits from
0
Peripheral
Vector
Figure 3. Z80 16-Bit Pointer (Interrupt Starting Address)
UM008101-0601
Counter/Timer Channels