Z80 Datasheet, PDF (101/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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CPU to a temporary register. It normally identifies the interrupting device
and it can also identify the cause of the interrupt (actually the current state
of certain status bits). The I Register of the Z80 CPU (when the CPU is
programmed to Mode 2 state) has the upper byte of a 16-bit address, which
is formed with the interrupt vector, and this address points to a jump table
entry in memory.
The jump table location in memory contains an address that is read to the
CPU’s program counter (Figure 33b). This address points to the first
instruction of the interrupt service routine, which then begins executing. In
most DMA applications, the CPU’s interrupt service routine contains
instructions that write control bytes back into the DMA through a register
in the CPU (Figure 33c).
In CPU environments without interrupt vectors, the CPU must poll each
peripheral or an external register to determine tristate device interrupted
and why.
UM008101-0601
Direct Memory Access