Z80 Datasheet, PDF (264/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Synchronous Transmit
Initialization
The system program must initialize the transmitter with the following
parameters: odd or even parity, x1 clock mode, 8-bit or 16-bit sync char-
acter(s), CRC polynomial, Transmitter Enables, Request To Send, Data
Terminal Ready, interrupt modes, and transmit character length. WR4
parameters must be issued before WR1, WR3, WR5, WR6, and WR7
parameters or commands.
One of two polynomials, CRC -16(X¹⁶ + X¹⁵ + X² + 1) or SDLC (X¹⁶ +
X¹² + X⁵ + 1), may be used with synchronous modes. In either case (SDLC
mode not selected), the CRC generator and checker are reset to all 0s. In the
transmit initialization process, the CRC generator is initialized by setting
the Reset Transmit CRC Generator command bits (WR0). Both the trans-
mitter and the receiver use the same polynomial.
Transmit Interrupt Enable or Wait/Ready Enable can be selected to transfer
the data. The External/Status interrupt mode is used to monitor the status of
the CLEAR TO SEND (CTS) input as well as the Transmit Underrun/EOM
latch. Optionally, the Auto Enables feature can be used to enable the trans-
mitter when CTS is active. The first data transfer to the Z80 SIO can begin
when the External/Status interrupt occurs (CTS status bit set) or immediately
following the Transmit Enable command (if the Auto Enables modes is set).
Transmit data is held marking after reset or if the transmitter is not
enabled. Break may be programmed to generate a spacing line that begins
as soon as the Send Break bit is set. With the transmitter fully initialized
and enabled, the default condition is continuous transmission of the 8-bit
or 16-bit sync character.
Data Transfer and Status Monitoring
UM008101-0601
Serial Input/Output