Z80 Datasheet, PDF (40/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Loading The Time Constant Register
A Time Constant Data Word is written to the Time Constant register by the
CPU. This event occurs on the I/O Write Cycle following that of the
channel control word. The Time Constant Data Word may be any integer
value in the range 1-256 (Table 6). If all eight bits in this word are zero, it is
interpreted as 256. If a Time Constant Date Word is loaded to a channel
already in operation, the down-counter continues decrementing to zero
before the new time constant is loaded.
Table 6. Time Constant Register
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Loading The Interrupt Vector Register
The Z80 CTC operates with the Z80 CPU programmed for mode 2
interrupt response. When a CTC interrupt request is acknowledged, a 16-bit
pointer is formed to obtain a corresponding interrupt service routine
starting address (Figure 8). The upper eight bits of this pointer are provided
by the CPU’s I register; the lower eight bits are provided by the CTC in the
form of an interrupt vector unique to the requesting channel (Figure 8). For
further details, see “CTC Interrupt Servicing” on page 27.
The five high-order bits of the interrupt vector are written to the CTC in
advance as part of the initial programming sequence. The CPU writes to the
I/O port address corresponding to the CTC Channel 0. A 0 in bit 0 signals
the CTC to load the incoming word into the interrupt vector register. When
the interrupt vector is placed on the Z80 data bus, the interrupt control logic
of the CTC automatically supplies a binary code in bits 1 and 2 identifying
which of the four CTC channels is to be serviced.
UM008101-0601
Counter/Timer Channels