Z80 Datasheet, PDF (162/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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the Z80 bus, to function. These functions are described in the following
sections, and design solutions are offered:
• Bus request/release mechanisms
• Bus characteristics
• Interrupt request, acknowledge, and return
Bus Request/Release Mechanisms
The most fundamental characteristic that distinguishes the Z80 DMA from
other monolithic DMACs is its full control of the system bus during its
active state. Therefore, processors using the DMA must be able to give up
control of the system bus, including address, data, and the control lines
MREQ, IORQ, RD, and WR (or their equivalents). Some processors have
no mechanism for freeing the bus. Others, including the 6800, have rudi-
mentary bus control facilities, but because of their internal dynamic logic
implementations, cannot relinquish control for indefinite periods of time.
This makes them difficult to interface to the DMA.
Many popular microprocessor CPUs, however, do have adequate bus
control facilities, and some are very similar to the Z80 BUSREQ and
BUSACK signals. For instance, the 8080, 8085, and 8086 signals HOLD
and HLDA are very close approximations.
The active levels of HOLD and HLDA are positive rather than negative,
and variations exist in timing. But the use of HOLD and HLDA allows the
address and data bus drivers to be put into their high-impedance states. In
8080 systems using an 8238 to demultiplex commands, the MEMW,
MEMR, IOW, and IOR control lines can be floated using the BUSEN
input. With the 8085, a tristate decoder allows decode or disable corre-
sponding signals. The 8086 and its support chips also tristate their control
signals when HLDA is active.
UM008101-0601
Direct Memory Access