Z80 Datasheet, PDF (312/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Read Registers
The Z80 SIO contains three registers, RR2-RR0 (Figure 122 through
Figure 124), that are read to obtain the status information for each channel,
with the exception of RR2-Channel B. The status information includes error
conditions, interrupt vector, and standard communications-interface signals.
To read the contents of a selected read register other than RRD, the system
program must first write the pointer byte to WR0, in exactly the same way
as a write register operation. Then, by executing an input instruction, the
contents of the addressed read register can be read by the CPU.
The status bits of RR0 and RR1 are carefully grouped to simplify status
monitoring. For example, when the interrupt vector indicates that a Special
Receive Condition interrupt occurred, all the appropriate error bits can be
read from a single register (RR1).
Read Register 0
This register contains the status of the receive and transmit buffers; the
DCD, CTS, and SYNC inputs; the Transmit Underrun/EOM latch; and the
Break/Abort latch.
Table 31. Read Register 0 Rx and Tx Buffers
D7
D6
IDS
Break/ Transmit CTS
Abort Underrun
EOM
D4
Sync/
Hunt
Buffer
Empty
D3
DCD
D2
D1
D0
Transmit Interrupt Receive
Pending Pending Character
(Ch.A available
only)
Receive Character Available (DO)
This bit is set when at least one character is available in the receive buffer;
it is reset when the receive FIFO is empty.
UM008101-0601
Serial Input/Output