Z80 Datasheet, PDF (30/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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33
34
N/C
CS1
CLK/TRG3
CLK/TRG2
N/C
N/C
CLK/TRG1
CLK/TRG0
N/C
+5V
N/C
44
1
CMOS
Z80 CTC
22
IEO
IORQ
N/C
ZC/TO2
ZC/TO1
N/C
ZC/TO0
N/C
RD
GND
D7
12
11
Figure 7. 44-Pin Quad Flat Pack Pin Assignments
Bit 7–Bit 0
System Data Bus (bidirectional, tristate). This bus is used to transfer all
date and command words between the Z80 CPU and the Z80 CTC. There
are eight bits on this bus, of which bit 0 is the least-significant. CSI CSO
Channel Select (input, active High). These pins form a 2-bit binary address
code for selecting one of the four independent CTC channels for an I/O
Write or Read. (See Table 4).
UM008101-0601
Counter/Timer Channels