Z80 Datasheet, PDF (302/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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282
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
Interrupt
V4
Vector
V5
V6
V7
Figure 116. Write Register 2
Write Register 3
WR3 (Figure 117) contains receiver logic control bits and parameters.
(Table 20)
Table 20. Write Register 3 Logic Control
D7
Receiver Bits/
Chars
D3
Receiver CRC
Enable
D6
D5
Receiver Bits/Char Auto Enables
0
D2
D1
Address Search Sync Char Load
Mode
Inhibit
D4
Enter Hunt Phase
D0
Receiver Enable
Receiver Enable (D0)
A 1 programmed into this bit allows receive operations to begin. Set this bit
only after all other receive parameters are set and the receiver is completely
initialized.
UM008101-0601
Serial Input/Output