Z80 Datasheet, PDF (64/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Classes of Operation
The Z80 DMA has three basic classes of operation, and two of the classes
are each broken into subclasses as follows:
• Transfers of data between any two DMA ports:
– Sequential transfers (flow-through)
– Simultaneous transfers (flyby)
• Searches for a particular bit pattern within a byte at a single DMA port
• Combined transfers and searches between any two DMA ports:
– Sequential transfer/search
– Simultaneous transfer/search
Figure 18 illustrates these classes. The two subclasses of transfers are illus-
trated at the top; the search-only class is depicted in the middle, and the two
subclasses of transfer-while-searching are featured at the bottom. In all
cases, the DMA assumes full control of the system address, data, and
control buses while transferring or searching a given byte. The DMA ports
are the source and destination of data; a port is used here to mean either
memory or an I/O device.
In sequential transfers, which are sometimes called flow-through transfers,
each byte transfer includes a read cycle followed by a write cycle. The DMA
reads the byte via the data bus to an internal register and sustains the byte on
the data bus into the subsequent write cycle. In a Z80 CPU environment, as
well as in certain other CPU environments, sequential DMA transfers can be
implemented with no external logic between the DMA and the CPU.
In simultaneous transfers, which are sometimes called flyby transfers,
each byte is simultaneously read from the source into the DMA and
written from the source directly to the destination in a single machine
cycle. These transfers, therefore, occur at twice the rate of sequential
transfers, but they require at least one external logic package to cause the
proper signals to appear simultaneously on the control bus (see “The
actual number of bytes transferred is one more than specified by the block
UM008101-0601
Direct Memory Access