Z80 Datasheet, PDF (305/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
285
Table 22. Write Register 4 Rx and Tx Control
D7
Clock
Rate 1
D6
D5
D4
D3
Clock Sync Sync Stop
Rate 0 Modes 1 Modes 0 Bits 1
D2
Stop
Bits 0
D1
Parity
Even/
Odd
D0
Parity
Parity (D0)
If this bit is set, an additional bit position is added to transmitted data and is
expected in receive data. This added bit position is in addition to those bits
specified in the bits/character control. In the Receive mode, the parity bit
received is transferred to the CPU as part of the character, unless eight bits/
character is selected.
Parity Even/Odd (D1)
If parity is specified, this bit determines whether the bit is sent and checked
as even or odd (1 = even).
Stop Bits 0 and 1 (D2 and D3)
These bits determine the number of stop bits added to each asynchronous
character sent. The receiver always checks for one stop bit. A special mode
(00) designates that a synchronous mode is to be selected.
Table 23. Stop Bits
D3
Stop Bits 1
0
0
1
1
D2
Stop Bits 0
0
1
0
1
Result
Sync modes
1 stop bit per character
1-1/2 stop bits per character
2 stop bits per character
UM008101-0601
Serial Input/Output