Z80 Datasheet, PDF (247/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
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busses, as well as being a part of the Z80 interrupt structure. As a peripheral
to other microprocessors, the Z80 SIO offers valuable features such as non-
vectored interrupts, polling and simple handshake capabilities.
The first part of the following functional description describes the interac-
tion between the CPU and Z80 SIO. The second part introduces its data
communications capabilities.
I/O Capabilities
The Z80 SIO offers the choice of Polling, Interrupt (vectored or non-
vectored), and Block Transfer modes to transfer data, status, and control
information to and from the CPU. The Block Transfer mode can be imple-
mented under CPU or DMA control.
Polling
The Polled mode avoids interrupts. Status registers RR0 and RR1 are
updated at appropriate times for each function being performed, for example,
CRC Error status valid at the end of the message. All the Z80 SIO interrupt
modes must be disabled to operate the device in a polled environment.
While in Polling sequence, the CPU examines the status contained in RR0
for each channel. The RR0 status bits serve as an acknowledge to the Poll
inquiry. The two RR0 status bits D0 and D2 indicate that a receive or
transmit data transfer is needed. The status also indicates Error or other
special status conditions (see “Programming” on page 272). The Special
Receive Condition status contained in RR1 does not have to be read in a
Polling sequence because the status bits in RR1 are accompanied by a
Receive Character Available status in RR0
Interrupts
The Z80 SIO offers an elaborate interrupt scheme to provide fast interrupt
response in real-time applications. As covered earlier, Channel B registers
WR2 and RR2 contain the interrupt vector that points to an interrupt service
UM008101-0601
Serial Input/Output