Z80 Datasheet, PDF (147/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Note: The actual number of bytes transferred is one more than specified by the block length.
* These entries are necessary only in the case of a fixed destination address.
Z80 DMA and CPU
As a member of the Z80 Family, the Z80 DMA’s signals and timing are
compatible with those of the Z80 CPU. As bus master, the DMA has read-
and write-cycle characteristics identical to those of the Z80 CPU, thereby
simplifying system design. In addition, variable timing features allow the
system designer to interface memories and I/O devices more easily with
non-standard capabilities or requirements. The DMA can shorten its read-
or write-cycle timings for higher performance or lengthen and tailor control
signals to accommodate slower devices. Because these features are under
programmed control, the hardware configuration is not affected by changes
in cycle and control signal timings.
Interconnection
In small systems, or where the Z80 DMA shares a board with the CPU,
most of the pins on the DMA may be connected directly to the corre-
sponding CPU pins. These pins include the address bus (A15-A0), the data
bus (D7-D0), and the control signals MREQ, IORQ, RD, and WR. The
interrupt request and bus request signals, INT and BUSREQ, may also be
connected directly to the CPU, in common with corresponding open-drain
outputs from other devices. The priority daisy-chains for these functions are
described in an earlier chapter and are illustrated in Figure 31 and
Figure 37.
Power, ground, and clock signals are also common to the CPU and DMA,
but extra care must be taken to provide low impedance paths and adequate
decoupling. A 300 Ohms pull-up from a TTL clock driver output may be
adequate for small systems operating at the 2.5 MHz rate, but the increased
loadings and speeds in larger high-performance systems require active pull-
UM008101-0601
Direct Memory Access