Z80 Datasheet, PDF (154/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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+5V
MWR
CLK
BUSACK
D
CLK
PRE
Q
1/2
74LS74
DMWR
Figure 53. Delaying the Leading Edge of MWR
Bus Buffering
Microcomputer systems using DMA often include large memories, many
peripheral devices, or occupy several circuit cards. In these cases, the
system buses and control signals require buffering to increase drive capa-
bility and noise margin and to decrease delay times.
The need for buffering within a single circuit card can be estimated by
comparing drive capabilities of bus master devices (CPU and DMA) to
loadings presented by all inputs and outputs connected to the buses. Both
static (DC current) and dynamic (capacitive drive) requirements must be
considered. When driving a motherboard or other cards, buffering is a prac-
tical necessity.
If the bus master devices (CPU and DMAs) are on the same card, they can
share buffers for address, data, and control buses to other cards. Otherwise,
each card’s bus interfaces require buffering.
Address lines are unidirectional and can be buffered by many common
devices such as 74LS244 and 74LS367 (non-inverting tristate buffer/
drivers) or 74LS240 and 74LS366 (inverting tristate buffer/drivers). The
tristate enable inputs on buffers such as these allow the bus to be isolated
UM008101-0601
Direct Memory Access