Z80 Datasheet, PDF (274/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

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Table 7. Bisync Receive Mode (Continued)
Function
Typical Program Steps
Comments
Data Transfer And When Interrupt on first character During the hunt mode, the SIO detects
Status Monitoring occurs, the CPU performs the
two contiguous characters to establish
following:
synchronization. The CPU establishes
• Transfers data byte to CPU
the DMA Mode and all subsequent data
• Detects and sets appropriate
control characters (in CPU)
flags for
characters are transferred by the
controller. The controller is also
programmed to capture special
DMA
• Includes/Excludes data byte in CRC _{characters (by examining only the bits}
checker
that specify ASCII or EBCDIC control
• Updates pointers and other
characters) and interrupt the CPU upon
parameters
detection. In response, the CPU
• Enables Wait/Ready for DMA
operation
• Enables DMA controller
examines the status or control characters
and takes appropriate action, such as
CRC enable update.
• Returns from Interrupt
When Wait/Ready becomes active, the
DMA controller performs the
following:
• Transfers Data Byte to memory
• Interrupts CPU if a special character
is captured by the DMA controller
• Interrupts the CPU if the last
character of the message is detected
For Message Termination, the CPU
performs the following:
• Transfers RR1 to the CPU
• Sets Ack/Nak Reply Flag based on
CRC result
The SIO interrupts the CPU for error
condition, and the error routine aborts
the present message, clears the error
condition, and repeats the operation.
• Updates pointers and parameters
• Returns from Interrupt
UM008101-0601
Serial Input/Output