Z80 Datasheet, PDF (317/330 Pages) Zilog, Inc. – Z80 CPU PERIPHERALS

Z80 CPU Peripherals
User Manual
297
Read Register 1
This register contains the Special Receive condition status bits and Residue
codes for the I-Field in the SDLC Receive Mode.
Table 32. Read Register 1 Special Receive Condition Status
D7
D6
DS
End of CRC/ Receiver
Frame Framing Overrun
(SDLC) Error Error
D4
Parity
Error
D3
D2
D1
D0
Residue Residue Residue All sent
Code 2 Code 1 Code 0
All Sent (D0)
In asynchronous modes, this bit is set when all the characters have
completely cleared the transmitter. Transitions of this bit do not cause inter-
rupts and it is always set in synchronous modes.
Residue Codes 0, 1, and 2 (D3-D1)
In SDLC receive mode, these three bits indicate the length of the I-field,
when the I-field is not an integral multiple of the character length. These
codes are only meaningful for a transfer in which the End-of-Frame bit is
set (SDLC). For a receive character length of eight bits per character, the
codes signify the following:
Table 33. Residue Codes
I-Field Bits in
Residue Code Residue Code Residue Code I-Field Bits in Second
2
1
0
Previous Byte Previous Byte
1
0
0
0
3
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6
1
0
1
0
7
UM008101-0601
Serial Input/Output